Interesting military/commercial surplus gear is common on eBay, but rarely does an item's coolness-per-dollar figure reach that of these little microwave synthesizers. Appearing in several auction lots for US $19.99 each, these user-friendly modules are capable of phase-locking almost any YIG-tuned oscillator in the 2-12 GHz range. They're intended for use with the Stellex/Endwave 6755-725F and 6755-726F YTOs, also widely available on eBay, but are easily modified for use with other YTO models.
Some key features include:
- Operates from +5V and +8.5V DC supplies
- Based on popular LMX2326 2.8-GHz PLL chip with simple three-wire serial control interface
- Includes onboard divide-by-4 prescaler driven by YIG coupling loop and two MMIC gain stages
- Includes onboard TCVCXO (temperature-compensated voltage-controlled crystal oscillator) with approximately +/- 100 ppm tuning range
- Power opamps with 1A current capability can drive YIG tuning coils directly
- Many handy extras are provided by the seller, such as schematics, device data sheets, and pinouts
The documentation provided by the seller was very helpful, but it omitted a couple of key specs such as the intended phase-detector comparison frequency, as well as important performance characteristics including phase noise and lockup time. Get the comparison frequency wrong, and your synthesizer may work only in "spread spectrum" mode! So, before contemplating any embedded applications for the Stellex synthesizer, it made sense to develop an experimental application that could control the synth from my Windows PC, with the goal of determining the missing specs empirically.
Several recent projects have used the LMX2326 PLL and similar chips, so I already had a good head start at programming the synthesizer. My control program, stellex.exe, along with all of the schematics and other documentation I received from the seller, may be downloaded here.
Full C++ source code, compatible with both Microsoft Visual Studio 2005 for Win32 and AVR-GCC for Atmel microcontrollers, is also included in this zipfile.
To run stellex.exe on a Windows 2000 or XP box, you will need to connect the synthesizer to a parallel port on your PC as follows:
| 20-pin connector on board | DB-25 LPT port connector | Signal |
|---|---|---|
| 12 | 4 | LATCH |
| 10 | 3 | DATA |
| 7 | 2 | CLOCK |
| 14 | 15 | LOCK_DETECT |
| 1,2,3,4,17,18 | 18-25 | GROUND |
Next, you'll need to determine the base address of the parallel port. This can usually be done by inspecting the first Input/Output Range entry in the Resources tab for your parallel port in the Windows Device Manager. It will usually be 378, 278, or 3BC.
Once you know this base address, you should be able to run a command of the form stellex 3bc at a DOS prompt or as a Start->Run command from the taskbar.
The synthesizer should lock within a few hundred milliseconds at most. If, instead, you
see a continuous line of periods (. . .), you'll need to do some troubleshooting. Search for
a few of the different ways to verify that your parallel-port base address is correct.
Try setting the port to standard mode, rather than ECP/EPP. Hang a scope on pin 2 (the first data line) to watch for
activity when stellex.exe starts up.
One possible source of trouble: in order to achieve reliable lockup detection, I had to remove a 1K resistor from my synthesizer board between pin 14 of the LMX2326 (Fo/Ld) and pin 14 of the 20-pin IDC header. This resistor does not appear on the schematic. Replace it with a much smaller one (100 ohms or so), or a jumper. Otherwise, the pullup resistors in your PC's parallel-port interface may be too "stiff" to allow the lock-detect line to be read.
Another problem lies in the reversal of connections to pins 19 and 20 in at least some versions of the 6942A_2 ("CODELOADER INTERFACE CABLE") diagram provided with the synthesizer. Pin 19 is the 10 MHz output sample from the TCVCXO, while pin 20 is the TCVCXO's tuning control voltage. These pins are shown correctly on the other two diagrams ("BEST_INTERFACE_SCHEMATIC2" and "GOOD_INTERFACE_SCHEMATIC1").
Other than these minor issues,
the connections shown on the CODELOADER_CABLE.pdf interface cable schematic are all that's necessary to run stellex.exe.
It didn't take long to determine that the synthesizer's intended comparison frequency appears to be 250 kHz. To begin with, the comparison frequency has to be an integer factor of the 10 MHz clock frequency, because the LMX2326's reference divider accepts only integer R values. If we limit ourselves to Fcomp options that result in whole-number output frequencies when multiplied by arbitrary integer N values, a relatively-small set of possibilities emerge. These, in turn, are easy to compare with a spectrum analyzer:
- 5 MHz: Loop unstable
- 1 MHz: Loop locks, but with large 'ears' a few kHz from the carrier
- 500 kHz: Relatively-stable, less peaking
- 250 kHz: Seems optimal; stable and consistent behavior during frequency transitions
- 200 kHz: Also relatively stable
- 100 kHz: Very slow locking/stabilization times observed
- 50 kHz: Loop unstable
The phase-noise measurements below were taken
with the 250 kHz Fcomp value.
It proved difficult to stabilize the TCVCXO sufficiently during the
90-second phase noise measurement sweep. The yellow trace reflects the best of several attempts.
Eventually, I gave up and removed the TCVCXO from my board, installing a third SMA jack and
an LT1016 high-speed comparator in its place to allow the board to operate from an
external 10-MHz clock source. This modification, visible at right, is a worthwhile one for
most applications... unless you plan to stabilize the onboard TCVCXO with its own PLL!
Once the board was operating from a stable 10 MHz reference, another problem with the phase-noise measurement process became apparent: the synthesizer was too clean for the HP 8566B spectrum analyzer to measure accurately at offsets beyond about 5 kHz from the carrier. Note the increasing convergence of the blue analyzer-baseline trace and the green measurement trace in the graph above. This situation is worse than it looks: a proper noise baseline trace, if taken at the measurement frequency of 9 GHz where harmonic mixing is used, would be at least 6 dB higher than these 100-MHz traces.
A partial solution to this measurement difficulty can be reached by opening up the HP 8566B and replacing its own YIG synthesizer reference with a cleaner version obtained from an HP 8662A signal generator.
Briefly, when the analyzer is tuned to center frequencies near 9 GHz, an internal "M/N" reference signal is generated at approximately 189.565 MHz. The M/N signal is used as a basis for phase-locking the analyzer's local oscillator, so any improvement in M/N spectral purity will improve the analyzer's baseline noise performance. (See HP Application Note 283-3, chapter 11, for an overview of this technique as it applies to the physically-similar HP 8672A microwave signal generator.)
The purple baseline trace reflects this improvement, as does the red measurement trace...
not a dramatic difference, but enough to reveal that the Stellex synthesizer is performing a few
dB better than initially observed. The peaking characteristics in the analyzer's baseline trace, even the improved one,
are still clearly visible in the measurement trace at offsets between 10 and 30 kHz.
Important: If you add an external
clock input to your board, keep both its signal path and ground return away from the PLL chip's RF input circuitry, including the YIG input jacks and prescaler/buffer MMICs. You may have trouble getting the synthesizer to lock if there's any
clock-induced ground bounce or crosstalk. Avoid doing what I did in this photo, where the ground return from the 10 MHz clock
ran near the RF input traces. Ideally, any clock-input hardware and wiring should be added near the opposite edge of the board, as
seen in my later prototypes below.
April 9, 2009
Here's a compact microcontroller implementation of a YIG synthesizer built with the Stellex board. This version was constructed around an Atmel ATTiny2313. Despite the chip's stripped-down specifications (2KB code space, 128 bytes SRAM), it was still possible to write the firmware in C/C++ using the free WinAVR GCC package. You can download this code here.
Even if you're using a different microcontroller (PIC, etc.) in your project, I'd recommend basing your firmware development on the stellavr.cpp module in this zipfile. It's much easier to read, debug, and customize than the Windows version mentioned above.
Another Atmel implementation used similar firmware with the
ATmega163. I used the ATmega163 here because it was handy; this version of
the synthesizer could also have used an ATTiny2313 or similar low-end part.
Below, an interior view reveals the same BCD thumbwheel switch and MC100EL16 input-clock conditioner that the earlier project used, along with
the necessary regulators to allow operation from a single +12V supply. The clock shaper circuit
is identical to the input stage in an earlier comb generator project.
A toggle switch allows selection of an external 10 MHz source or the board's own 10 MHz TCXO. Again, be careful to keep the LMX2326's clock-reference and RF paths separate.
In-band phase noise is about -65 dBc/Hz, or approximately 15 dB better than the composite (AM+PM) noise measurement made with PN.EXE above.
This suggests that a substantial AM noise component is present. Ordinarily, measurement comparisons between PN.EXE and the HP 3048A system
agree much better than this.
The clock source for this measurement was the 10 MHz output from a Trimble Thunderbolt.
Technical Correspondence
April 9, 2009 Evert Verduin sends along some photos of his 10 GHz synthesizer based on the PIC 12F629:
